Method for improving the sidewall stoichiometry of thin film capacitors

ABSTRACT

A method for ion implantation of high dielectric constant materials with dopants to improve sidewall stoichiometry is disclosed. Particularly, the invention relates to ion implantation of (Ba,Sr)TiO 3 (BST) with Ti dopants. The invention also relates to varying the ion implantation angle of the dopant to uniformly dope the high dielectric constant materials when they have been fabricated over a stepped structure. Additionally, the invention relates to forming a capping layer over a horizontal portion of the BST film to reduce excess dopant from being implanted into the horizontal section of the BST film. The invention also relates to integrated circuits having a thin film high dielectric material with improved sidewall stoichiometry used as an insulating layer in a capacitor structure.

FIELD OF THE INVENTION

[0001] The invention relates generally to ion implantation of highdielectric constant materials with dopants to improve the sidewallstoichiometry of high dielectric thin films deposited over 3-Dformations. Particularly, the invention relates to ion implantation ofTi into a (Ba,Sr)TiO₃(BST) film by varying the implantation angle of thedopant to improve the sidewall stoichiometry the BST film. The inventionalso relates to integrated circuits having a doped thin film highdielectric material, used, for example, as an insulating layer in acapacitor.

BACKGROUND OF THE INVENTION

[0002] High dielectric constant (HDC) materials have manymicroelectronic applications, such as DRAMs, embedded DRAMs, SRAMs,FeRAMS, on-chip capacitors and high frequency capacitors. Typically,these applications employ HDC materials in a capacitive structure,although the present invention may be used to make an HDC thin film withimproved properties which is not part of a capacitor.

[0003] To facilitate construction of larger DRAMs with correspondinglysmaller memory cells, capacitor structures and materials which can storethe necessary charge in smaller spaces are needed. One of the mostpromising avenues of research to achieve this goal is the area of HDCmaterials. HDC materials have dielectric constants of greater than about50. Examples of particular HDC materials are metal oxide materials suchas, lead zirconate titanate (PZT), barium titanate (BaTiO₃), strontiumtitanate (SrTiO₃), and barium strontium titanate (BST). It is desirablethat such a material, if used for DRAMs and other microelectronicsapplications, be formable over an electrode and underlying structure(without significant harm to either), have low leakage currentcharacteristics and long lifetime, and, for most applications, possess ahigh dielectric constant. The present invention relates to a method offorming a HDC film, for example, a BST dielectric film, with improvedsidewall stoichiometry.

[0004] While BST materials have been manufactured in bulk formpreviously, the physical and electrical properties of the material isnot well understood when BST is formed as a thin film (generally lessthan 5 um) on a semiconducting device. Methods to form the (Ba,Sr)TiO₃material include deposition by a metal organic chemical vapor deposition(MOCVD) process using appropriate precursors. Typical MOCVD depositionof BST utilizes the precursors ofBa(bis(2,2,2,6-tetramethyl-3,5-heptanedionate))₂-tetraethylene glycoldimethyl ether;Sr(bis(2,2,2,6-tetramethyl-3,5-heptanedionate))₂-tetraethylene glycoldimethyl ether andTi(bis(isopropoxy))₂bis(2,2,2,6-tetramethyl-3,5-heptanedionate)₂. Aliquid delivery system mixed, metered and transported the precursors atroom temperature and high pressure to a heated zone, where theprecursors were then flash vaporized and mixed with a carrier gas,typically argon, to produce a controlled temperature, low pressure vaporstream. The gas stream was then flowed into a reactor mixing manifoldwhere the gas stream mixed with oxidizer gases. Typically the oxidizergases were O₂ and N₂O. The mixture of the gas stream and the oxidizergases then passed through a shower head injector into a depositionchamber. In the MOCVD deposition, both the ratio of the concentrationsof the metalorganic compounds in the vaporized liquid and the depositionconditions determine the final film stoichiometry. However, the MOCVDBST deposition process suffers from the inhomogeneity in stoichiometry(A:B site ratio) on 3-D structures.

[0005] In addition, in submicron microcircuits such as DRAM capacitors,particular constraints are placed on BST thin film. First, the annealingtemperature for BST thin films must generally be kept far below thetemperatures commonly used for sintering bulk BST ceramics (generallyless than 700° C. vs. typically greater than 1100° C. for bulk BST) toavoid damage to the underlying device structure. Thus, the grainnucleation and growth kinetics of the BST crystal lattice is inhibitedresulting in smaller grain sizes. Second, the desired film thickness inmicroelectronic applications may be much less than 5 um (preferablybetween about 0.05 um and about 0.1 um). It has been found that mediangrains sizes generally less than half the BST film thickness arerequired to control dielectric uniformity and avoid shorted capacitors.Finally, when a BST film is formed in a microelectronic application suchas a container or a stud, the sidewall components of the film generallycontains less titanium than is present in the horizontal components ofthe container or stud formation. The percentage of titanium in the filmis critical to the physical end electrical functionality of the film. Ithas been shown that the titanium must be between about 50% to about53.5% of the BST film in order for the film to have beneficial physicaland electrical properties Thus, a method for producing a HDC materialsuch as BST in a thin film structure having good dielectric propertiesand uniform titanium content is needed.

SUMMARY OF THE INVENTION

[0006] The present invention overcomes the drawbacks of the conventionalmethods and provides an ion implanted high dielectric constant materialhaving improved sidewall stochiometry. Particularly, the presentinvention overcomes the observed Ti-stoichiometry variation on thesidewalls of 3-D structures for MOCVD (BST) thin film capacitors. Theinventor has observed that MOCVD BST thin films exhibit a deviation inA:B site ratio on the sidewalls of the trench or stud type structures.Typically, at these regions, at % Ti in the thin film is less than thedesired value. The present invention overcomes these problems byimplanting Ti ions by ion implantation after MOCVD process of BST. Withthis technique, it is possible to tailor the Ti composition in BSTfilms, preferably on the sidewalls, by appropriate ion implantationangles.

[0007] The present invention also provides a method for tailoring thesidewall stoichiometry by providing a capping layer over the 3-Dstructure before Ti ion implantation thereby adjusting the sidewallstoichiometry of the BST film with ion implantation by varying theimplantation angles.

[0008] The above and other advantages and features of the invention willbe more clearly understood from the following detailed description whichis provided in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 is a schematic view of one embodiment of an apparatus usedin the present invention.

[0010]FIG. 2 is a cross-sectional view of a container capacitor formedaccording to the present invention.

[0011]FIG. 3 is a cross-sectional view of an ion implantation of thesidewalls of a semiconductor device having a stud formation.

[0012]FIG. 4 is a cross-sectional view of an ion implantation of thesidewalls of a semiconductor device having a stud formation according toa second embodiment of the present invention.

[0013]FIG. 5 is a cross-sectional view of an ion implantation step of aportion of a semiconductor device having a stud formation at aprocessing step subsequent to that shown in FIG. 4.

[0014]FIG. 6 is a cross-sectional view of an ion implantation step of aportion of a semiconductor device having a stud formation at aprocessing step subsequent to that shown in FIG. 5.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The terms wafer or substrate used in the description include anysemiconductor-based structure having an exposed silicon surface in whichto form the contact electrode structure of this invention. Wafer andsubstrate are to be understood as including silicon-on insulator (SOI)technology, silicon-on-sapphire (SOS) technology, doped and undopedsemiconductors, epitaxial layers of silicon supported by a basesemiconductor foundation, and other semiconductor structures.Furthermore, when reference is made to a wafer or substrate in thefollowing description, previous process steps may have been utilized toform regions/junctions in the base semiconductor structure orfoundation. It should also be understood that the term wafer orsubstrate may relate to a base semiconductor structure having undergoneprocessing steps to arrive at a semiconductor platform which may undergofurther processing.

[0016] The term “metal oxide” or “high dielectric constant material(HDC)” used herein means a material of the general form ABO₃ where A andB are cations. The term is intended to include materials were A and Brepresent multiple elements; for example, it includes materials of theform A′A″BO₃, AB′B″O₃, and A′A″B′B″O₃, where A′, A″, B′ and B″ aredifferent metal elements. Preferably, A, A″, A″, are metals selectedfrom the group of metals consisting of Ba, Bi, Sr, Pb, Ca, and La, andB, B′, and B″ are metals selected from the group consisting of Ti, Zr,Ta, Mo, W, and Nb. Preferably the metal oxide is a perovskite. Many ofthese metal oxides are ferroelectrics; however the present invention isnot so limited.

[0017] As will be understood by those skilled in the art, mostcrystalline materials having an ABO₃ formula are perovskite crystallinecompounds. These structures ideally have a unit cell forming a simplecubic structure including A-type cations at the corners of a cube, aB-type cation at the centroid of the cube, and oxygen atoms entered ateach facial plane of the cube; however, this idealized structure mayvary considerably with temperature. Other forms of perovskite-typecompounds can be classified, for example, as orthombic, pseudocubic,pseudotetragonal, rombohedral, and tetragonal.

[0018] Some materials falling within the class of ABO₃, such as bariumstrontium titanate (BST) exhibit electrical properties that are oftenvery different when measured from bulk ceramics, as compared to the thinfilm materials (i.e., those less than about ten microns thick) that areused in integrated circuits. Bulk ceramics are typically sintered attemperatures reaching from 1400° C. to 1500° C., and this hightemperature tends to produce a correspondingly high degree ofdefect-free crystallization. On the other hand, thin films are generallynot sintered above about 900° C. to 1100° C. due to the potential forbreakdown of integrated circuit wiring, layer interdiffusion, andcracking. Thin films are most often deposited by conventional sputteringtechniques, e.g., radio frequency or DC magnetron sputtering. On amicroscopic level, these techniques can provide clumped areas of massedmaterials having nonuniform thicknesses, stratified layers that areimproperly mixed to non-homogeneic proportions that are incapable offorming proper average crystals according to the mixture of ingredients.Accordingly, those attempting to replicate bulk ceramic behavior in thinfilm electronic components have often been unable to duplicate theseparameters, even if the electron transfer mechanism remains the samebetween the two thicknesses of materials.

[0019] The Ba/Sr ratio of BST should be about 70/30 allowing thematerial to operate in the paraelectric region for DRAM applicationssince this will reduce the complexity of understanding the material'sresponse. Therefore, the importance of Ba/Sr ratio in the BST materialis controlling the curie temperature (Tc) to be nearly room temperature,thus giving the material the advantage of having a high dielectricconstant since the dielectric constant exhibits a peak near Tc whileallowing the material to be in the paraelectric region for the operatingtemperature of the DRAM cell. By maintaining a Ba/Sr ratio of about70/30, the danger of shifting to ferroelectric state by a possible shiftin temperature (less than room temperature) is eliminated. This isbecause the material exhibits a curie-point at room temperature forBa/Sr:70/30, but does not go to the ferroelectric phase untiltemperatures of about 190° K.

[0020] Additionally, it is important that the percentage of Ti in theBST thin film is between about 50% and about 53.5%. When the percentageof Ti in the BST thin film is outside this range, the BST thin film willexhibit poor. physical and electrical properties. For example, when thepercentage of Ti in the BST thin film is outside the prescribed range,the BST thin film will exhibit a poor dielectric constant and also willexhibit increased current leakage.

[0021] Since the stoichiometry of BST formed on the sidewalls oftrenches can deviate from the target values, it is necessary to maintainthe stoichiometry at the sidewalls. This becomes a serious issue fordeep trenches (e.g., 10:1 aspect ratios) since properties such asdielectric constant, leakage, relaxation and resistance degradation willdeviate at the sidewalls from other locations on a semiconductor. Withthe present invention sidewalls can be doped to achieve the desiredstoichiometries by using appropriate implant angles. Thus, withappropriate doping levels, sidewall stoichiometries can be tailored toachieve desired physical properties.

[0022] The metal oxides or high dielectric constant material accordingto the present invention arc doped by ion implantation of dopants intothe host lattice of the metal oxide or HDC material. Ion implantation isa well known process for the implantation of dopant elements into amaterial. The dopants are selected from Ba, Bi, Sr, Pb, Ca, and La forthe A site and Ti, Zr, Ta, Mo, W, and Nb for the B-site based on theparticular HDC material. For example, in a BST metal oxide, the A-sitecan be doped with additional Ba or Sr while the B-site can be doped withadditional Ti to tailor the particular stoichiometry of the thin film.

[0023] Capacitor size requirements presently constitute a limitingfactor in further reductions of DRAM cell size. A reduction in DRAM cellsize is essential to further significant increases in DRAM celldensities for use in an integrated circuit, but this size reductionadvantage will require a further reduction in the size of the cellcapacitor. Reduction of the capacitor size can be achieved by increasingthe dielectric constant of the material used in the dielectric layer ofthe capacitor, in order to permit the use of a smaller surface area in acapacitor having the desired dielectric properties. Prior methods forincreasing the dielectric constant of materials have met with failurebecause these methods also increased the leakage current and thecorresponding conductive current density of the dielectric material atfixed bias voltages. Excessive leakage current or conductive currentdensity renders the material unfit for capacitors in integrated circuitsand, in particular, unfit for capacitors in DRAM cells. It remains aproblem in the field to increase the dielectric constant of materials,even fbr high dielectric constant material, such as BST, withoutsignificantly increasing the leakage current.

[0024] By doping the HDC material with A or B ions it is possible tomaintain the dielectric constant of the material as well as preventcurrent leakage from the material. An exemplary apparatus used in theprocess for ion implantation according to one embodiment of the presentinvention is described below. It is to be understood, however, that thisapparatus is only one example of many possible different arrangementsthat may be used to implant dopants according to the invention. Theinvention is not intended to be limited by the particular apparatusdescribed below.

[0025] Referring now to FIG. 1, a closed ion implant system 10 for ionimplanting semiconductor wafers in accordance with the method of theinvention is shown. The ion implant system 10 includes an ion implanter16. The construction for the ion implanter 16 shown in FIG. 1 is merelyillustrative as other types of ion implanter constructions would also besuitable. In the illustrative embodiment, the ion implanter 16 includesa wafer holder 40 for receiving a wafer 18 from the transport channel 26and for holding the wafer for implantation. The wafer 18 has a HDC thinfilm layer formed thereon as discussed above. The ion implanter 16includes an ion source 42, an analyzing magnet 44, an acceleration tube46, a focus structure 48, and a gate plate 50. The ion implanter 16 isin flow communication with a suitable vacuum source (not shown) such asa turbo molecular pump. This generates a vacuum within the processchamber of the ion implanter 16. With this arrangement an ion implantbeam 52 is focused on the high dielectric constant thin film on thesurface of the wafer 18 for implanting a desired dopant (such as, forexample, Ba, Bi, Sr, Pb, Ca, and La for the A site and Ti, Zr, Ta, Mo,W, and Nb for the B-site based on the particular HDC material) into thecrystal lattice structure of the high dielectric constant thin film.After ion implantation the wafer 18 is transferred from the wafer holder40 to another transport channel 28. At the transport channel 28, thewafer 18 is discharged from the system 10.

[0026] At this point, the wafer 18 has a conductive layer 60 formed of asuitable conductive material with a doped dielectric film layer 65formed over the conductive layer 60. A second conductive layer 68 isthen formed over doped dielectric film layer 65 to form the containercapacitor structure as shown in FIG. 2. The conductive layers 60, 68 maybe formed of any conductive material such as metals, i.e., Pt, Ru, Ir,Pd, Au or conductive oxides such as a ruthenium oxide (RuO_(x)) or aniridium oxide (IrO_(x)). The doped dielectric film layer 65 is formed bydoping a HDC material as described above.

[0027] Reference is now made to FIG. 3. This figure shows arepresentative view of a stud capacitor formation according to thepresent invention. Dopant levels of the HDC film, such as BST, formed onthe sidewalls 102 of a stud 100 can deviate from the target values. Thisbecomes a serious issue for deep trenches (e.g., 10:1 aspect ratios) orstuds as shown in FIG. 3 since properties such as dielectric constantand leakage will deviate at the sidewalls from the values for theseproperties in the horizontal portions of the device. According to thepresent invention the HDC, e.g. BST, dielectric layer 105 formed over aconductive layer 120 on the sidewalls 102 can be doped to achieve thedesired stoichiometries by appropriate implant angles 110-119 byappropriate movement of wafer holder 40. A second electrode (not shown)may then be formed over the HDC, e.g. BST, layer 105 to arrive acapacitor structure. Thus, with appropriate doping levels, the HDC layer105 overlying the conductive layer 120 on sidewalls 102 can be tailoredto achieve desired physical properties.

[0028] Reference is now made to FIG. 4. This figure shows arepresentative view of a second embodiment of the present invention.Dopant levels of BST formed on the sidewalls 202 of a stud 200 candeviate from the target values. This becomes a serious issue for deeptrenches (e.g., 10:1 aspect ratios) or studs as shown in FIGS. 4-6 sinceproperties such as dielectric constant and leakage will deviate at thesidewalls from the values for these properties in the horizontalportions of the device. A passivation layer 250 is deposited over thehorizontal sections of the stud 200 as shown in FIG. 4. The passivationlayer 250 may be formed of any material such that the BST dielectriclayer 205 formed under the passivation layer 250 is significantlyshielded form ion implantation.

[0029] Reference is now made to FIG. 5. According to the secondembodiment of the present invention the BST dielectric layer 205 formedover a conductive layer 220 on the sidewalls 202 can be doped to achievethe desired stoichiometries by appropriate implant angles 210-219. Theappropriate movement of wafer holder 40, as shown in representativeapparatus in FIG. 1, is used to effectuate the appropriate implantangels 210-219. The passivation layer 250 prevents dopant from beingimplanted into the BST film that overlies the horizontal regions of thestud 200.

[0030] The passivation layer 250 is then removed from the horizontalsurfaces of the stud 200 as shown in FIG. 6. A second electrode (notshown) may then be formed over BST layer 205 to arrive at a capacitorstructure. Thus, with appropriate doping levels, the BST layer 205overlying the conductive layer 220 on sidewalls 202 can be tailored toachieve desired physical properties.

[0031] The present invention provides a method for ion implantation ofHDC materials with dopants to reduce film leakage and improve resistancedegradation. The invention also provides a method for varying the ionimplantation angle of the dopant to uniformly dope the high dielectricconstant materials when they have been fabricated over a steppedstructure.

[0032] It should again be noted that although the invention has beendescribed with specific reference to DRAM memory circuits and containercapacitors, the invention has broader applicability and may be used inany integrated circuit, such as, for example in a capacitor. Similarly,the process described above is but one method of many that could beused. Furthermore, although the invention has been described withreference to BST as a preferred HDC material which can be used in theinvention, the invention has more widespread applicability to any HDCmaterial. Accordingly, the above description and accompanying drawingsare only illustrative of preferred embodiments which can achieve thefeatures and advantages of the present invention. It is not intendedthat the invention be limited to the embodiments shown and described indetail herein. The invention is only limited by the spirit and scope ofthe following claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A method for maintaining the stoichiometry of ahigh dielectric constant thin film material formed on a threedimensional substrate, said method comprising: providing a substratehaving a first level and a second level, wherein said first and secondlevels are connected by a sidewall region between said first and secondlevels; forming a high dielectric constant thin film material on saidsubstrate; and doping said high dielectric thin film material with adopant by ion implantation, wherein said high dielectric thin filmmaterial is doped to maintain the stoichiometry of said high dielectricthin film material.
 2. The method according to claim 1, wherein saidhigh dielectric thin film material is doped by varying the implant angleof the dopant.
 3. The method according to claim 2, wherein said highdielectric constant thin film material is selected from the groupconsisting of BST, SBT, SrTio₃ and PZT.
 4. The method according to claim3, wherein said high dielectric constant thin film material is BST. 5.The method according to claim 4, wherein said dopants are selected fromthe group consisting of barium, strontium and titanium.
 6. The methodaccording to claim 2, wherein said high dielectric constant thin filmmaterial is a pervoskite of the formula ABO₃ where A represents metalsselected from Ba, Bi, Sr, Pb, Ca, and La, and B represents metalsselected from Ti, Zr, Ta, Mo, W, and Nb.
 7. The method according toclaim 6, wherein said doping step includes doping the A-site of saidhigh dielectric constant thin film material with a dopant selected fromthe group consisting of Ba, Bi, Sr, Pb, Ca, and La.
 8. The methodaccording to claim 6, wherein said doping step includes doping theB-site of said high dielectric constant thin film material with a dopantselected from the group consisting of Ti, Zr, Ta, Mo, W, and Nb.
 9. Themethod according to claim 6, wherein said pervoskite is barium strontiumtitanite and said doping step includes doping the A-site with a dopantselected from the group consisting of Ba, and Sr.
 10. The methodaccording to claim 6, wherein said pervoskite is barium strontiumtitanite and said doping step includes doping the B-site with Ti. 11.The method according to claim 10, wherein said barium strontium titaniteis doped with Ti to maintain a Ti percentage of from about 50% to about53.5% in said barium strontium titanite film.
 12. The method accordingto claim 11, wherein the ratio of Ba to Sr is about 70:30.
 13. A methodfor maintaining the stoichiometry of a high dielectric constant thinfilm material formed on a three dimensional substrate, said methodcomprising: providing a substrate having a first level and a secondlevel, wherein said first and second levels are connected by a sidewallregion between said first and second levels; forming a high dielectricconstant thin film material on said substrate; forming a capping layerover said first level and said second level of said substrate; anddoping said high dielectric thin film material formed on said sidewallswith a dopant by ion implantation, wherein said high dielectric thinfilm material is doped to maintain the stoichiometry of said highdielectric thin film material.
 14. The method according to claim 13,wherein said high dielectric thin film material is doped by varying theimplant angle of the dopant.
 15. The method according to claim 14,wherein said high dielectric constant thin film material is selectedfrom the group consisting of BST, SBT, SrTiO₃ and PZT.
 16. The methodaccording to claim 15, wherein said high dielectric constant thin filmmaterial is BST.
 17. The method according to claim 16, wherein saiddopants are selected from the group consisting of barium, strontium andtitanium.
 18. The method according to claim 14, wherein said highdielectric constant thin film material is a pervoskite of the formulaABO₃ where A represents metals selected from Ba, Bi, Sr, Pb, Ca, and La,and B represents metals selected from Ti, Zr, Ta, Mo, W, and Nb.
 19. Themethod according to claim 18, wherein said doping step includes dopingthe A-site of said high dielectric constant thin film material with adopant selected from the group consisting of Ba, Bi, Sr, Pb, Ca, and La.20. The method according to claim 18, wherein said doping step includesdoping the B-site of said high dielectric constant thin film materialwith a dopant selected from the group consisting of Ti, Zr, Ta, Mo, W,and Nb.
 21. The method according to claim 18, wherein said pervoskite isbarium strontium titanite and said doping step includes doping theA-site with a dopant selected from the group consisting of Ba and Sr.22. The method according to claim 18, wherein said pervoskite is bariumstrontium titanite and said doping step includes doping the B-site withTi.
 23. The method according to claim 22, wherein said barium strontiumtitanite is doped with Ti to maintain a Ti percentage of from about 50%to about 53.5% in said barium strontium titanite film.
 24. The methodaccording to claim 23, wherein the ratio of Ba to Sr is about 70:30. 25.A method for maintaining the stoichiometry of a BST high dielectricconstant thin film material formed on a three dimensional substrate,said method comprising: providing a substrate having a first level and asecond level, wherein said first and second levels are connected by asidewall region between said first and second levels; forming a BST highdielectric constant thin film material on said substrate; and dopingsaid BST high dielectric thin film material with a dopant by ionimplantation, wherein said BST high dielectric thin film material isdoped to maintain the stoichiometry of said BST high dielectric thinfilm material.
 26. The method according to claim 25, wherein BST highdielectric thin film material is doped by varying the implant angle ofthe dopant.
 27. The method according to claim 26, wherein said dopantsare selected from the group consisting of barium, strontium andtitanium.
 28. The method according to claim 27, wherein said BST highdielectric thin film material is doped with a dopant selected from thegroup consisting of Ba, and Sr.
 29. The method according to claim 27,wherein said BST high dielectric thin film material is doped with Ti.30. The method according to claim 29, wherein said BST high dielectricthin film material is doped with Ti to maintain a Ti percentage of fromabout 50% to about 53.5% throughout said BST high dielectric thin filmmaterial.
 31. The method according to claim 30, wherein the ratio of Bato Sr is about 70:30.
 32. A method for maintaining the stoichiometry ofa BST high dielectric constant thin film material formed on a threedimensional substrate, said method comprising: providing a substratehaving a first level and a second level, wherein said first and secondlevels are connected by a sidewall region between said first and secondlevels; forming a BST high dielectric constant thin film material onsaid substrate; forming a capping layer over said first and secondlevels of said substrate; and doping said BST high dielectric thin filmmaterial formed on said sidewalls of said substrate with a dopant by ionimplantation, wherein said BST high dielectric thin film material isdoped to maintain the stoichiometry of said high dielectric thin filmmaterial.
 33. The method according to claim 32, wherein BST highdielectric thin film material is doped by varying the implant angle ofthe dopant.
 34. The method according to claim 33, wherein said dopantsare selected from the group consisting of barium, strontium andtitanium.
 35. The method according to claim 34, wherein said BST highdielectric thin film material is doped with a dopant selected from thegroup consisting of Ba, and Sr.
 36. The method according to claim 34,wherein said BST high dielectric thin film material is doped with Ti.37. The method according to claim 36, wherein said BST high dielectricthin film material is doped with Ti to maintain a Ti percentage of fromabout 50% to about 53.5% throughout said BST high dielectric thin filmmaterial.
 38. The method according to claim 37, wherein the ratio of Bato Sr is about 70:30.
 39. A BST high dielectric constant thin filmmaterial having improved sidewall stoichiometry formed by the steps of:providing a substrate having at least one horizontal component and atleast one vertical component; forming a BST high dielectric constantthin film material on said substrate; and doping said BST highdielectric thin film material with a dopant by ion implantation, whereinsaid BST high dielectric thin film material is doped to maintain thestoichiometry of said BST high dielectric thin film material.
 40. TheBST high dielectric constant thin film material according to claim 39,wherein BST high dielectric thin film material is doped by varying theimplant angle of the dopant.
 41. The BST high dielectric constant thinfilm material according to claim 40, wherein said dopants are selectedfrom the group consisting of barium, strontium and titanium.
 42. The BSThigh dielectric constant thin film material according to claim 40,wherein said BST high dielectric thin film material is doped with adopant selected from the group consisting of Ba, and Sr.
 43. The BSThigh dielectric constant thin film material according to claim 40,wherein said BST high dielectric thin film material is doped with Ti.44. The BST high dielectric constant thin film material according toclaim 43, wherein said BST high dielectric thin film material is dopedwith Ti to maintain a Ti percentage of from about 50% to about 53.5%throughout said BST high dielectric thin film material.
 45. The BST highdielectric constant thin film material according to claim 44, whereinthe ratio of Ba to Sr is about 70:30.
 46. The BST high dielectricconstant thin film material according to claim 40, wherein said BST highdielectric thin film material is included in a DRAM cell.
 47. The BSThigh dielectric constant thin film material according to claim 40,wherein said BST high dielectric thin film material is formed in acapacitor.
 48. A BST high dielectric constant thin film material havingimproved sidewall stoichiometry formed by the steps of: providing asubstrate having a first level and a second level, wherein said firstand second levels are connected by a sidewall region between said firstand second levels; forming a BST high dielectric constant thin filmmaterial on said substrate; forming a capping layer over said first andsecond levels of said substrate; and doping said BST high dielectricthin film material formed on said sidewalls of said substrate with adopant by ion implantation, wherein said BST high dielectric thin filmmaterial is doped to maintain the stoichiometry of said high dielectricthin film material.
 49. The BST high dielectric constant thin filmmaterial according to claim 48, wherein BST high dielectric thin filmmaterial is doped by varying the implant angle of the dopant.
 50. TheBST high dielectric constant thin film material according to claim 49,wherein said dopants are selected from the group consisting of barium,strontium and titanium.
 51. The BST high dielectric constant thin filmmaterial according to claim 49, wherein said BST high dielectric thinfilm material is doped with a dopant selected from the group consistingof Ba, and Sr.
 52. The BST high dielectric constant thin film materialaccording to claim 49, wherein said BST high dielectric thin filmmaterial is doped with Ti.
 53. The BST high dielectric constant thinfilm material according to claim 52, wherein said BST high dielectricthin film material is doped with Ti to maintain a Ti percentage of fromabout 50% to about 53.5% throughout said BST high dielectric thin filmmaterial.
 54. The BST high dielectric constant thin film materialaccording to claim 53, wherein the ratio of Ba to Sr is about 70:30. 55.The BST high dielectric constant thin film material according to claim49, wherein said BST high dielectric thin film material is included in aDRAM cell.
 56. The BST high dielectric constant thin film materialaccording to claim 49, wherein said BST high dielectric thin filmmaterial is formed in a capacitor.
 57. A method for fabricating a highcapacitance thin film integrated circuit capacitor device, said methodcomprising: providing a substrate having a first level and a secondlevel, wherein said first and second levels are connected by a sidewallregion between said first and second levels; forming a first electrodeon said substrate; forming a BST high dielectric constant thin filmmaterial on said first electrode; doping said BST high dielectric thinfilm material with a dopant by ion implantation, wherein said BST highdielectric thin film material is doped to maintain the stoichiometry ofsaid BST high dielectric thin film material; and forming a secondelectrode on said BST high capacitance thin film layer to complete saidintegrated circuit capacitor.
 58. The method according to claim 57,wherein said B BST high dielectric thin film material is doped byvarying the implant angle of the dopant.
 59. The method according toclaim 58, wherein said dopants are selected from the group consisting ofbarium, strontium and titanium.
 60. The method according to claim 59,wherein said BST high dielectric thin film material is doped with adopant selected from the group consisting of Ba, and Sr.
 61. The methodaccording to claim 59, wherein said BST high dielectric thin filmmaterial is doped with Ti.
 62. The method according to claim 61, whereinsaid BST high dielectric thin film material is doped with Ti to maintaina Ti percentage of from about 50% to about 53.5% throughout said BSThigh dielectric thin film material.
 63. The method according to claim62, wherein the ratio of Ba to Sr is about 70:30.
 64. The methodaccording to claim 58, wherein said first and second electrodes areselected from the group consisting of Pt, Ru, Ir, Pd, Au rutheniumoxides, and iridium oxides.
 65. The method according to claim 58,wherein said integrated circuit capacitor is fabricated in a DRAM cell.66. A method for fabricating a high capacitance thin film integratedcircuit capacitor device, said method comprising: providing a substratehaving a first level and a second level, wherein said first and secondlevels are connected by a sidewall region between said first and secondlevels; forming a first electrode on said substrate; forming a BST highdielectric constant thin film material on said first electrode; forminga capping layer over said first and second levels of said BST highdielectric constant thin film material; doping said BST high dielectricthin film material formed on said sidewalls with a dopant by ionimplantation, wherein said BST high dielectric thin film material isdoped by varying the ion implantation implant angle to maintain thestoichiometry of said BST high dielectric thin film material; andremoving said capping layer and forming a second electrode on said BSThigh capacitance thin film layer to complete said integrated circuitcapacitor.
 67. The method according to claim 66, wherein said dopantsare selected from the group consisting of barium, strontium andtitanium.
 68. The method according to claim 67, wherein said BST highdielectric thin film material is doped with a dopant selected from thegroup consisting of Ba, and Sr.
 69. The method according to claim 67,wherein said BST high dielectric thin film material is doped with Ti.70. The method according to claim 69, wherein said BST high dielectricthin film material is doped with Ti to maintain a Ti percentage of fromabout 50% to about 53.5% throughout said BST high dielectric thin filmmaterial.
 71. The method according to claim 70, wherein the ratio of Bato Sr is about 70:30.
 72. The method according to claim 66, wherein saidfirst and second electrodes are selected from the group consisting ofPt, Ru, Ir, Pd, Au ruthenium oxides, and iridium oxides.
 73. The methodaccording to claim 66, wherein said integrated circuit capacitor isfabricated in a DRAM cell.
 74. An integrated circuit capacitor devicecomprising: a substrate having a first level and a second level, whereinsaid first and second levels are connected by a sidewall region betweensaid first and second levels; a first electrode provided on saidsubstrate; a doped BST high dielectric constant thin film materialprovided on said first electrode, said doped BST high dielectric thinfilm material being doped to maintain the stoichiometry of said BST highdielectric thin film material; and a second electrode provided on saidBST high capacitance thin film layer to complete said integrated circuitcapacitor.
 75. The integrated circuit capacitor device according toclaim 74, wherein said dopants are selected from the group consisting ofbarium, strontium and titanium.
 76. The integrated circuit capacitordevice according to claim 75, wherein said doped BST high dielectricthin film material is doped with a dopant selected from the groupconsisting of Ba, and Sr.
 77. The integrated circuit capacitor deviceaccording to claim 75, wherein said doped BST high dielectric thin filmmaterial is doped with Ti.
 78. The integrated circuit capacitor deviceaccording to claim 76, wherein said doped BST high dielectric thin filmmaterial is doped with Ti to maintain a Ti percentage of from about 50%to about 53.5% throughout said BST high dielectric thin film material.79. The integrated circuit capacitor device according to claim 78,wherein the ratio of Ba to Sr is about 70:30
 80. The integrated circuitcapacitor device according to claim 74, wherein said first and secondelectrodes are selected from the group consisting of Pt, Ru, Ir, Pd, Auruthenium oxides, and iridium oxides.
 81. The integrated circuitcapacitor device according to claim 74, wherein said integrated circuitcapacitor is a container capacitor.
 82. The integrated circuit capacitoraccording to claim 74, wherein said integrated circuit capacitor isformed over a stud.
 83. The integrated circuit capacitor according toclaim 74, wherein said integrated circuit capacitor is fabricated in aDRAM cell.
 84. An integrated circuit comprising: a substrate having afirst level and a second level, wherein said first and second levels areconnected by a sidewall region between said first and second levels; afirst electrode provided on said substrate; a doped BST high dielectricconstant thin film material provided on said first electrode, said dopedBST high dielectric thin film material being doped by angled ionimplantation; and a second electrode provided on said BST highcapacitance thin film layer to complete said integrated circuitcapacitor.
 85. The integrated circuit capacitor device according toclaim 84, wherein said dopants are selected from the group consisting ofbarium, strontium and titanium.
 86. The integrated circuit capacitordevice according to claim 85, wherein said doped BST high dielectricthin film material is doped with a dopant selected from the groupconsisting of Ba, and Sr.
 87. The integrated circuit capacitor deviceaccording to claim 85, wherein said doped BST high dielectric thin filmmaterial is doped with Ti.
 88. The integrated circuit capacitor deviceaccording to claim 86, wherein said doped BST high dielectric thin filmmaterial is doped with Ti to maintain a Ti percentage of from about 50%to about 53.5% throughout said BST high dielectric thin film material.89. The integrated circuit capacitor device according to claim 88,wherein the ratio of Ba to Sr is about 70:30
 90. The integrated circuitcapacitor device according to claim 84, wherein said first and secondelectrodes are selected from the group consisting of Pt, Ru, Ir, Pd, Auruthenium oxides, and iridium oxides.
 91. The integrated circuitcapacitor device according to claim 84, wherein said integrated circuitcapacitor is a container capacitor.
 92. The integrated circuit capacitoraccording to claim 84, wherein said integrated circuit capacitor isformed over a stud.
 93. The integrated circuit capacitor according toclaim 84, wherein said integrated circuit capacitor is fabricated in aDRAM cell.